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Type of Document Master's Thesis Author Patel, Virendra Rameshbhai, Author's Email Address patel.viren@gmail.com URN etd-12012005-180625 Title A Methodology for Hardware Design and Verification of Architectures for Channel Equalization Degree Master of Science Graduate Program Electrical Engineering Advisory Committee
Advisor Name Title Dr. Winser E. Alexander Committee Chair Dr. Eric Rotenberg Committee Member Dr. Rhett W. Davis Committee Member Keywords
- MIMO
- SVA
- SystemVerilog
- Channel Equalization
- Freqeuncy selective channels
- Flat fading channel
- Verification
- system-level design flow
- SystemC
- Least Mean Square
- productivity gap
- traditional design flow
- SystemC cycle accurate model
- Multi Input Multi Output
- System Level Design
- Hardware Design
- SystemVerilog Assertions
- cycle accurate
- Conjugate Gradient
- CDMA
- MIMO channels
Date of Defense 2005-10-27 Availability unrestricted Abstract PATEL, VIRENDRA R. A Methodology for Hardware Design and Verification of Architectures for Channel Equalization. (Under the guidance and direction of Dr. Winser E. Alexander.)
Hardware implementing wireless applications in today?s cellular systems has stringent requirements such as high speed, flexibility, and low power dissipation resulting in complex systems. These requirements have led to the development of systems on a single chip. Although this development promises a variety of design advantages, designers are facing new design difficulties and challenges while designing
these complex systems. Some of the design difficulties and challenges presented by the traditional design flow, in designing these complex systems, are increase in the simulation time, increase in the verification effort required, increase in the time to market, difficulty in exploring the design space, and
increase in the productivity gap.
In this research work, we introduce a new design flow that starts at the system level. The design flow, called the system-level design flow, promises to reduce the difficulty in exploring the design space, to reduce the simulation times, to reduce the verification and debugging time, to allow the definition of both hardware and software components of a design, and to allow defining the system at a high level of abstraction. To validate our design flow and its advantages, we consider a subsystem for a Wireless Communication System called a ?Multiple Input Multiple Output? (MIMO) wireless communication system for analysis. We consider the designs of channel equalization architectures for the MIMO wireless
communication system. We consider algorithms such as least mean square and iterative conjugate
gradient algorithms for implementing channel equalization. We design the algorithms using SystemC and Verilog. We consider the use of SystemVerilog to interface SystemC to the Verilog environment.
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