Title page for ETD etd-12012005-151541

Type of Document

Master's Thesis

Author

Elechitaya Suresh, Sanath Kumar ,

Author's Email Address

sanathes@gmail.com

URN

etd-12012005-151541

Title

System Level Design of a Turbo Decoder for Communication Systems

Degree

Master of Science

Graduate Program

Electrical Engineering

Advisory Committee

Advisor Name	Title
Dr. Winser E Alexander	Committee Chair
Dr. J. K. Townsend	Committee Member
Dr. William Rhett Davis	Committee Member

Keywords

Interleaver Design
Turbo Decoder
System Level Design
SystemC
RTL Design

Date of Defense

2005-10-12

Availability

unrestricted

Abstract

ELECHITAYA SURESH, SANATH KUMAR. System Level Design of a Turbo Decoder for Communication Systems. (Under the direction of Professor Winser E Alexander).

Advancements in silicon technology have heralded an increase in device densities and consequently design complexity. The increasing complexity of modern System on a Chip designs dictates a cohesive methodology for co-simulation at both high and low abstraction levels, effective design space exploration, system integration and high simulation speeds. A single unified design flow would avoid many of the shortcomings faced by the traditional RTL approach to design and verification.

This thesis investigated a SystemC based design methodology to model complex digital systems at multiple levels of abstraction. The SystemC language, which is a C++ class library, is a multi-paradigm language for hardware design and verification. The capabilities of SystemC in supporting timed behavior, hierarchy, concurrency,
and creation of fast executable specifications of the target design have been demonstrated in our work. It was our aim to clearly represent the ability of the proposed design flow to capture and validate the details of a design at the system level of abstraction, starting with an abstract Functional Verification level, working our way
through to the Cycle Accurate level. This was exemplified by the design of a complex
Iterative Turbo Decoder algorithm as a prototype system to test our design flow. We compared the decoder behavior at the system level using SystemC and at the RTL using Verilog 2001. We found that simulations performed at the system level executed
much faster than simulations at the RTL. We used the system level design to estimate round-off errors without having to refine our design to the RTL. We demonstrated the ease of architectural exploration using SystemC by implementing two classes of interleavers for the Turbo Decoder: the Pseudo Random and the 3GPP Standard Interleaver. We also performed a detailed power and area analysis on the RTL model using the SSHAFT tool. We established a single language framework that allows analysis of the trade-offs between hardware and software implementation models.

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