Search the Collection|Browse Subjects|Services|Library Information|Community |News & Events MY LIBRARY: Library Account | My Course Reserves | My Alerts

Type of Document	Master's Thesis
Author	Vijaychand, Shubha ,
Author's Email Address	svijayc@unity.ncsu.edu
URN	etd-11072002-172455
Title	Time-step Control in Transient Circuit Analysis
Degree	Master of Science
Graduate Program	Electrical Engineering
Advisory Committee	Advisor Name Title Dr Michael Steer Committee Chair
Keywords	truncation error time-step control variable time-step
Date of Defense	2002-07-23
Availability	unrestricted
Abstract VIJAYCHAND , SHUBHA,. Time Step Control in Transient Analysis. (Under the direction of Michael B. Steer) The time-step control algorithm has a dramatic impact on the accuracy and simulation time in transient circuit simulation. A new time-step control algorithm is presented based on a novel estimation of the truncation error. The new truncation error estimation uses di®erence between Backward Euler and Trapezoidal numerical integration techniques. The results of this technique are compared with The traditional SPICE-like approach implemented in fREEDA. Results for the solution of a Soliton line and Mesfet circuit are presented.
Files	Filename       Size       Approximate Download Time (Hours:Minutes:Seconds)     28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access    etd.pdf 609.66 Kb 00:02:49 00:01:27 00:01:16 00:00:38 00:00:03