| Type of Document |
Master's Thesis |
| Author |
Arkesh, Vikram , |
| URN |
etd-08252003-103528 |
| Title |
FPGA Implementation of a Low Power Doppler Invariant BFSK Receiver |
| Degree |
Master of Science |
| Graduate Program |
Electrical Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Dr. Paul D. Franzon |
Committee Chair |
| Dr. J Keith Townsend |
Committee Member |
| Dr. Rhett Davis |
Committee Member |
|
| Keywords |
- FPGA
- CORDIC
- Fast Fourier Transform
- Frequency Shift Keying
|
| Date of Defense |
2003-07-31 |
| Availability |
unrestricted |
Abstract
A non coherent frequency shift keying (FSK) receiver architecture is designed potentially for low power applications. The receiver incorporates a 16 point Fast Fourier Transform (FFT) for symbol detection and can withstand large Doppler shifts. Almost all the design units of the receiver are digital designs for better power efficiency and reliability. The receiver functions on one bit data processing and supports data rates of 10kbps, 1kbps and 100bps. Co-ordinate rotation (CORDIC) algorithm is used for complex multiplications while computing FFT, evading the use of power hungry multipliers.
The design and simulation of the receiver is carried out in MATLAB/SIMULINK. The MATLAB model is translated to a XILINX FPGA hardware model using system generation features of the XILINX development system. The hardware model is synthesized to a virtex-2 XILINX FPGA and various performance parameters are extracted. A control system for symbol and timing detection is designed and modeled in VHDL, synthesized to XILINX hardware and interfaced to the receiver.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
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etd.pdf |
1.76 Mb |
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