Title page for ETD etd-05192003-125609

Type of Document

Dissertation

Author

Kim, Indong ,

Author's Email Address

ikim2@unity.ncsu.edu

URN

etd-05192003-125609

Title

Device Fabrication and Characterization for Alternative Gate Stack Devices

Degree

PhD

Graduate Program

Electrical Engineering

Advisory Committee

Advisor Name	Title
Carlton M. Osburn	Committee Chair
John R. Hauser	Committee Member
Jon-Paul Maria	Committee Member
Veena Misra	Committee Member

Keywords

MOSFET
Scaling
High-K
Metal Gate
Silicate
HfO2

Date of Defense

2003-05-07

Availability

unrestricted

Abstract

Abstract
Kim, Indong. Device Fabrication and Characterization for Alternative Gate Stack Devices. (Under the direction of Dr. Carlton M. Osburn)

Aggressive scaling has continued to improve MOSFET transistor performance. An effective oxide thickness (EOT) less than 1.0nm is required for future technology nodes. However, tunneling currents of SiO2 become quite prominent below 1.5nm, leading to high leakage current. High-K dielectrics are required to reduce this leakage. A thicker dielectric reduces the probability of electron and/or hole tunneling through the gate dielectric and therefore the tunneling current. The use of metal gate electrodes is one of the technologies assumed in ITRS roadmap to circumvent the high sheet resistance and depletion associated with poly-Si gates.
This dissertation covers the following research areas. First, projections of gate leakage currents for future ITRS nodes were made. High-K dielectrics which dramatically lower leakage will be needed for low standby power applications around year 2005. Secondly, NMOS and PMOS devices with alternative gate stacks were fabricated and evaluated using a new non-self aligned process. PVD HfO2 with an equivalent oxide thickness of 1.2 nm had a channel mobility comparable to SiO2.
The effect of post metallization annealing of devices having PVD HfO2 was studied. Forming gas (10% H2 / 90% N2) annealing at 400�C enhanced drive current and channel mobility for devices having 1.2nm HfO2 gate dielectrics by eliminating interface states. PMA using 10% deuterium for 1.2nm HfO2 gate dielectrics resulted in larger enhancement drive currents and device channel mobility as compared to forming gas anneals.
The stability of poly-Si gated HfO2 (~1.2nm EOT) dielectrics was also assessed after constant current stressing of the gate. The changes in device properties were measured as a function of stress time and stress current. With forming gas annealed HfO2, positive shifts in the threshold voltage exhibited a power law dependence on the injected charge (DVt � QINJ 0.1).
Finally, the properties of dilute Hf silicate were studied. A leakage minima was found at an intermediate Hf silicate (45~75% HfO2) composition. Nitirdation inhibited oxygen diffusion through Hf silicate dielectrics, and resulted in lower EOTs (10% lower) for nitrided samples.

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