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Title page for ETD etd-01192005-172005


Type of Document Dissertation
Author Lazar, Heather Rebecca,
Author's Email Address hrlazar@ncsu.edu
URN etd-01192005-172005
Title Mobility Degradation of Advanced CMOS Devices
Degree PhD
Graduate Program Electrical Engineering
Advisory Committee
Advisor Name Title
Dr. Veena Misra Committee Chair
Dr. Eric Vogel Committee Member
Dr. Gerry Lucovsky Committee Member
Dr. Griff Bilbro Committee Member
Dr. Jayant Baliga Committee Member
Keywords
  • MOSFET
  • high k dielectrics
  • metal gate electrodes
  • bulk trapping
  • interface traps
  • interfaces
  • charge pumping
  • mobility
Date of Defense 2005-01-31
Availability unrestricted
Abstract
As alternative materials are being pursued for CMOS gate dielectric scaling to

below 1 nm, challenges arise that warrant investigation for greater understanding.

Mobility values, in particular, of ultra thin SiO2 and high k MOSFET devices have

been reported to be low and the reason behind this degradation is still unclear.

Furthermore, a study on the effects of implementation of candidate metal gate

electrodes on mobility values has not yet been performed. Since many of the

properties of these materials are still under scrutiny, accurate determination of their

electrical and analytical characteristics is needed.

In this work, an investigation of the mobility of several candidate metal gate

electrodes on high k dielectrics was performed and compared with that of SiO2 and

polysilicon. This work was separated into two components. The first study

compared three metal gate electrodes on HfO2 with that of SiO2 in the 2 nm EOT

range fabricated at North Carolina State University. Standard and advanced

electrical characterization, including Dit and bulk trapping characteristics, was

performed including two and three level charge pumping and other pulsed methods.

It was found that mobility values were very similar for the metal gate electrodes both

on high k and SiO2. The second study analyzed the mobility values for aggressively

scaled EOT (< 2nm) devices with a metal and polysilicon gate electrode indicating a severely degraded mobility. Both the interface and the bulk trapping behavior of

these devices were also analyzed and used to correct the mobilities. However,

corrections to mobility for both trapping and interface trap density did not recover the

mobility of these devices. The mechanism responsible for mobility degradation

beyond trapping in these aggressively scaled MOSFETs will be discussed. Finally,

steps necessary to enhance mobility will be presented.

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