| Type of Document |
Master's Thesis |
| Author |
Joseph, Balu , |
| Author's Email Address |
balujoseph@ieee.org |
| URN |
etd-01062003-204633 |
| Title |
High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling |
| Degree |
Master of Science |
| Graduate Program |
Electrical Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Dr. Wentai Liu |
Committee Chair |
| Dr. Gianluca Lazzi |
Committee Member |
| Dr. Rhett Davis |
Committee Member |
|
| Keywords |
- high-speed transceiver
- equalization
- CDR
- serial-link
- SERDES
- multi-level
- 4-PAM
|
| Date of Defense |
2002-12-20 |
| Availability |
unrestricted |
Abstract
The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
etd.pdf |
5.39 Mb |
00:24:57 |
00:12:50 |
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